Imperas Joins RISC-V Foundation: Virtual Platforms and Models Now Available, Demonstrations at the 6th RISC-V Workshop in Shanghai, China and the 2017 Design Automation Conference
OXFORD, England--(BUSINESS WIRE)--#54thDAC--Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their membership in the RISC-V Foundation, along with Imperas virtual platform and model support for the RISC-V architecture, available now. Imperas will demonstrate these embedded software development solutions at the 6th RISC-V Workshop in Shanghai, China, May 8-11, 2017 and also at the Design Automation Conference (DAC) 2017 in Austin, Texas June 18-22, 2017.
The RISC-V Foundation drives the adoption of the new RISC-V instruction set architecture (ISA), set to become a standard open architecture for industry implementations, and directs its future development. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.
“Imperas believes that the customizable, open RISC-V architecture is a boon to the embedded electronics industry, and that delivering our next-generation models, virtual platforms and software development methodology will help accelerate its adoption,” said Simon Davidmann, president and CEO of Imperas.
Rick O’Connor, Executive Director, RISC-V Foundation commented: “Imperas virtual platforms and models for the open RISC-V architecture will enable early software development, long before hardware is available. These RISC-V Imperas virtual platforms lower software development costs, increase quality, improve time to market, and reduce software development risks.”
Imperas has developed and released open source models of the RISC-V RV32I and RV64I cores through the Open Virtual Platforms™ (OVP™) website. These RISC-V models, together with other OVP models, APIs and the OVPsim virtual platform simulator, enable the building and customization of instruction accurate models and platforms for custom SoC subsystems, full SoCs, or larger systems for software development.
Imperas will demonstrate RISC-V virtual platforms and models, including software debug, verification, analysis, and profiling tools, and deliver a technical paper, Modern Software Development Methodology for RISC-V Devices, at the 6th RISC-V Workshop in Shanghai China on May 8-11, 2017.
- Demonstrations will show virtual platforms (often called virtual prototypes) for RISC-V software porting and development: it’s all about the software.
- The Imperas paper: Modern Software Development Methodology for RISC-V Devices, explores how the success of RISC-V is dependent upon the easy porting and bring up of legacy software, and the easy development of software for new RISC-V devices being built. The embedded systems community is increasingly adopting virtual prototypes, or virtual platforms, to achieve higher software quality and reduce software engineering schedules. Instruction-accurate virtual prototypes offer advantages over hardware-based development platforms in controllability, observability, repeatability, and ease of automation. Virtual platforms can also be available to the entire software team months before hardware platforms can be used. This paper discusses the complementary nature of virtual and hardware platforms as well as Continuous Integration (CI) and Continuous Test (CT) development methodology.
Imperas will also demonstrate its virtual platforms for RISC-V software porting and development at DAC 2017 in Austin, Texas, June 18-22, 2017.
The addition of RISC-V models expands existing Imperas and Open Virtual Platforms (OVP) platform support to over 170 processor models across a wide variety of vendors. For the latest list of Imperas models, please see www.OVPworld.org.
For more information about RISC-V, see https://riscv.org.
For more information about Imperas, please see www.imperas.com.
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Larry Lapides, 925-519 1234